| | Setting Up Verible for Verilog with Neovim (danielmangum.com) |
| 1 point by hasheddan on Nov 3, 2023 | past |
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| | A Particularly Gnarly Case of Go's Non-Nil Interfaces (danielmangum.com) |
| 2 points by hasheddan on Oct 20, 2023 | past | 1 comment |
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| | How LUTs Are Used as Storage Elements on an FPGA (danielmangum.com) |
| 2 points by hasheddan on Oct 14, 2023 | past |
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| | The Value of Livestreaming Long-Term Projects (danielmangum.com) |
| 3 points by hasheddan on Oct 6, 2023 | past | 2 comments |
|
| | When Does Vivado Infer Bram? (danielmangum.com) |
| 1 point by hasheddan on Oct 1, 2023 | past |
|
| | Microprocessors Are Tiny, but They Can’t Fit in Your Head (danielmangum.com) |
| 1 point by hasheddan on Sept 2, 2023 | past |
|
| | A Brief Retrospective on SPARC Register Windows (danielmangum.com) |
| 4 points by hasheddan on Aug 21, 2023 | past |
|
| | How to Dissect a Critical Hacker News Comment (danielmangum.com) |
| 4 points by hasheddan on Aug 9, 2023 | past |
|
| | A Single-Cycle 64-Bit RISC-V Register File (danielmangum.com) |
| 84 points by hasheddan on Aug 4, 2023 | past | 33 comments |
|
| | Single-Cycle and Multicycle Do Not Describe Processor Performance (danielmangum.com) |
| 1 point by hasheddan on July 28, 2023 | past |
|
| | Why Create a New Instruction Set Architecture? (danielmangum.com) |
| 2 points by hasheddan on July 21, 2023 | past |
|
| | A Three Year Bet on Chip Design (danielmangum.com) |
| 1 point by hasheddan on July 19, 2023 | past |
|
| | RISC-V Bytes: Semihosting with Zephyr on an ESP32 (danielmangum.com) |
| 2 points by hasheddan on May 30, 2023 | past |
|
| | RISC-V Bytes: Zephyr Before Main (danielmangum.com) |
| 3 points by hasheddan on April 28, 2023 | past |
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| | RISC-V Bytes: Zephyr on the ESP32 (danielmangum.com) |
| 3 points by hasheddan on April 17, 2023 | past |
|
| | RISC-V Bytes: Exploring a Custom ESP32 Bootloader (danielmangum.com) |
| 98 points by hasheddan on April 9, 2023 | past | 8 comments |
|
| | Where does the kubelet mount volumes? (danielmangum.com) |
| 1 point by hasheddan on March 18, 2023 | past |
|
| | How Kubernetes API Server Watch Caches Work (danielmangum.com) |
| 2 points by hasheddan on Feb 13, 2023 | past |
|
| | Kubernetes API Server Adventures: The Storage Interface (danielmangum.com) |
| 3 points by disadvantage on Jan 28, 2023 | past |
|
| | K8s API Server Adventures: The Storage Interface (danielmangum.com) |
| 1 point by steilpass on Jan 24, 2023 | past |
|
| | The Kubernetes Storage Interface (danielmangum.com) |
| 2 points by hasheddan on Jan 23, 2023 | past |
|
| | How RISC-V Timer Interrupts Work (danielmangum.com) |
| 81 points by hasheddan on Dec 27, 2022 | past | 14 comments |
|
| | Stack Use After Return (danielmangum.com) |
| 2 points by azhenley on Dec 27, 2022 | past |
|
| | RISC-V Bytes (danielmangum.com) |
| 82 points by hasheddan on Dec 3, 2022 | past |
|
| | Go 1.19's register calling convention demonstrated with RISC-V assembly (danielmangum.com) |
| 2 points by Shugyousha on Nov 9, 2022 | past |
|
| | Go 1.19 RISC-V Register-Based Calling Convention (danielmangum.com) |
| 2 points by hasheddan on Aug 18, 2022 | past |
|
| | RISC-V Register-Based Calling Convention in Go 1.19 (danielmangum.com) |
| 3 points by hasheddan on Aug 8, 2022 | past |
|
| | RISC-V Bytes: Stack Use After Return in C, Go, and Rust (danielmangum.com) |
| 3 points by hasheddan on Aug 2, 2022 | past |
|
| | RISC-V Stack Use After Return in C, Go, and Rust (danielmangum.com) |
| 2 points by hasheddan on Aug 1, 2022 | past |
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| | RISC-V Weak Memory Ordering (danielmangum.com) |
| 2 points by hasheddan on July 27, 2022 | past | 2 comments |
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| More |
