Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?
The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it's just a commercial name for a generation.
The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial name.
They are not even comparable across companies. For example, TSMC 7nm process technology has 91 MTr/mm², Intel's 10 nm prosess technology has 100 MTr/mm². Samsung 10nm has 52 MTr/mm². (MTr/mm² refers to millions of transistors per mm²).
Very interesting, thank you. So we're basically not nearly as close to "true" 7nm as I thought? Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?
According to this video using an electron scanning microscope on amd and Intel chips, the “7nm” or “10nm” number does not measure anything, and is effectively a process version number for marketing. From memory there is no single number for measuring transistors or efficiency, transistor density is useful, but it doesn’t tell you the performance or power usage.
Moore's law always was an economic roadmap. Everything in the semiconductor industry is (was) planned around the transistor density doubling every two years, from hardware investments, to market segmentation, to microarchitecture design, to software optimizations. So I think it makes sense that they go on with pushing transistor density from generation to generation, and convey it to the public using names it is already familiar with.
It's right that power has severely limited performance despite increasing the transistor density lately. Maybe we'll once again get better with adiabatic computing?
Both performance and power usage are physically functions of transistor density. Assuming the apples-to-apples comparison of similar transistor counts, operating TDPs, and processor designs.
>Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?
If you will forgive the expression. Yes and No.
Yes in that TSMC has ideas / plans scaling all the way to 0.8nm, targeting 2030. That is only a few steps above what you described as true 7nm.
No in that no one knows if it will work. We know Quantum Tunnelling will hit some day, some where, some how, at some percentage.
Remember you are talking about leading edge Semi-Conductor manufacturing. Nothing like this has ever been done before.
It is a bit like telling me 5G today was possible when I was researching on first gen 3G two decades ago. If you describe to me with theory I will have properly said yes..... but it is hard to imagine how it will actually be implemented.
Technically it’s figured out. Gate-all-around has been experimentally demonstrated at pitches less than FinFET. The primary problem is, who is going to pay it. The economics are very tough at these 1s of nm nodes but hopefully that’s only a transitory problem.
You are talking about GAA at 2nm, I was talking about sub 1nm ( Node naming ) Tech. Which the OP was referring to "true" 7nm or Gate pitch / metal pitch at sub 7nm. We are still quite far away from figuring those out.
But yes, I agree the economics model is tough as I have been stating on various forums for years. That is part of the reason why we see Semi-conductors consolidation, like Marvell, Broadcom.
My best guess is that some time in 2026/ 28 we might have to stretch the cycle to three years instead of two. Giving more time to amortised those cost. But HyperScaler Cloud Market seems to be not limited by any R&D funding so I am actually quite optimistic we could see the current 2 year cadence all the way to 2030. Anything beyond is just too hard to predict or infer.
To make transistors smaller, and not just draw them with finer resolution, the industry will need a new way of controlling the channel. FinFET got us here. Most likely gate-all-around will be the technique that gets the “true” geometries smaller.
State of the art non EUV photo lithography uses light with a 193 nm wavelength. 20nm is significantly below that which would imply usage of highly advanced lithography techniques like multiple patterning. A chip manufactured with a 20nm resolution would involve dozens of masks which were created through electron-beam lithography. Just the mask set alone would cost millions of dollars.
The only hobbyist that I am aware of used a pretty nifty mask less technique but the resolution doesn't come close at all. I think you just mixed up your units.
Well, nano would be achievable via e-beam lithography, but photolithography is another beast: I'm pretty sure you need EUV at that size, with special (expensive) lenses that do not absorb the UV.
der8auer recently did a 3 part video on YouTube where he cut up AMD and Intel chips and looked at the transistors with an electron microscope. It sheads some light on meaning (or non-meaning) of the node names. Is also really interesting;
der8auer is basically the patron saint of PC overclocking, highly recommend his coverage of new hardware because he goes straight to doing interesting stuff and skips the usual review stuff that everyone else repeats.
I think we left the holy land of pc overclocking long ago.. this dude just showed us chemical coating of transistors.. Even Applied Science would be jealous.
The nm process numbers refer to the necessary dimensions of a theoretical planar transistor to achieve the same density as this process. Planar transistors haven't been used for at least a decade. To make matters worse there is no standardized planar transistor design so ultimately you cannot derive any meaning from these numbers other than as a fancy version number that tells you which process is newer. As many others have commented: It's much better to just look at overall transistor density.
FinFET and GAA (gate all around) are 3d transistor designs. Therefore you get impossible and purely theoretical planar numbers.
>That number has nearly zero bearing on the actual physical sizes of the chip's components.
AFAIK the reason behind this madness is that the number previously did correspond to feature size, but then they discovered methods of increasing transistor density without decreasing the size of the components. Since the feature size was used in marketing as a proxy for transistor density, they felt it was ultimately justified to decrease the number. After all, if your enhanced 32nm process provided the same transistor density as your competitor's 22nm process, why shouldn't you market your process as "22nm"?
Not the explanation you're looking for, but the CTO at TSMC co-invented the modern FinFET transistor. They've probably good a really good grasp on what issues block development of smaller features, and know how to find ways around those limits.
To make an analogy: I think a good way to think about it is that the 7nm node doesn't actually produce chips with 7nm features, it uses a "knife" (actually it's a lithography process) which is able to cut things as small as 7nm . That enables it to be more precise than a bigger "knife" so even though the size of the chip features is >7nm they are still able to be smaller than features cut with a 10nm "knife".
I don't actually know anything about chip production. But that's what I've picked up from HN.
One thing people are trying to convery every time this question comes up is that "7nm" is really just a marketing number, it's not tied to any particular physical dimension, and it's not how small the knife is able to cut.
The knife does get better, it's just not something that the Xnm node names measure directly.
That's kinda the idea. There are also several different layers each with its own resolution.
Also, well, that number isn't really the actual resolution of the finest layer, but is some "marketing processed" message that should give you an idea of the chips performance. It used to have the meaning you stated, but things changed a while ago.
for reference "TESCAN is a leading global producer and supplier of scanning electron microscopes, focused ion beam scanning electron microscopes and micro-CT solutions."
https://www.youtube.com/watch?v=3otqUu-7WUQ
Surprising for the flashy marketing style of the video it really explained to me the difference between FINFET, GAA and MBCFET really well.
Is Samsung and IBM stronger in structural R&D then they are at FABs?
FWIW I thought Samsung trademarked the name MBCFET. Not saying that is in fact worth much, just that I know for a fact Samsung has been concrete about when this is going to be a process customers can use.
On paper I don't think it's risky to say everyone is looking at GAAFETs and MBCFETs, they're the evolution of finFETs (okay, we have the fin, what about more than one fin? Okay, how about the channel is surrounded by the gate (Gate-All-Around)?)
How far along is everyone to making them commercially available with good yields, ¯\_(ツ)_/¯.
I think the surprising thing to me was TSMC has thus far (as of like a month ago) been of the mind "nah, finFETs are fine". But keep in mind, that was for their 3nm node, which this isn't.
TSMC has always had a conservative culture. They dont aim at x% of improvement per process node like Intel. GAA for 3nm has long been known to be not ready for 2022. They actually mentioned this in 2019. But it was only confirmed later at a conference that Anandtech picked it up. Mainstream media being an echo chamber decide to copy each other and the news spread like wild fire.
So it was only logical to push those improvements to 2nm.
You would have to be more specific about what you are claiming is untrue, that's a bit vague.
I'm aware of how TSMC felt about the prospects of GAA at 3nm, and their view of Samsung's yield prospects (i.e. not great).
Sure, it's logical to push GAA to the next node if you can, but part of TSMCs style is that they didn't even confirm that they were moving past fins until earlier this year.
I think that Intel is one step behind. They'll likely produce 7nm in 2024 which should be comparable with TSMC 5nm. But TSMC 5nm already available for Apple.
Having lived inside similar but much smaller dramas, it smells to me like Intel is titrating bad news.
There was a goal. The goal became PR. Someone in management began to believe the PR, and turned it into a promise, predicated on 'and then a miracle occurs' (the engineers figure out how to do some things that haven't been done before). The engineers keep trying to explain how nobody has done this before because you can't. To do so involves violating the laws of physics or Information Theory. Anyone who cracks this problem deserves a Nobel nomination, so that probably isn't us.
Middle management is stuck in the middle because someone has made promises we can't keep, and they either make it worse or help cover it up by playing for time.
You either solve a different problem that has similar behavior (or at least, until researchers discover Meltdown), or you slowly reset expectations until people are chronically grumpy but nobody is yelling.
There's almost no useful public insider information about the actual state of Intel's next gen technologies. We only know what is actually shipping and promises in PR slides. Sometimes I wonder if they don't know much more inside the company. There's roadmaps, projects, timelines, factories, teams, project managers, middle managers etc. but nobody has a clear picture of what's actually necessary and what's going to work in time. Engineers overpromise on the timeline, managers misreport "minor" hangups and upper management is left in the dark until it's much too late to change horses. Then there's stories of the old guard of engineers leaving but the replacements aren't getting up to speed quickly. Management even needs to consider outsourcing production to other companies because their homegrown engineering failed them time and time again lately. I really hope the core of the company is still solid and they get their act together soon.
Considering how poorly and inaccurately tech is portrayed in most other shows, I'm inclined to believe it's Mike Judge and the people that he chooses to listen to.
They have very good industry-insider consultants for the show. Plus, Mike Judge was a Silicon Valley engineer a long time ago, so I'm sure his experience gives him some insight into how to interpret the consultants and portray the modern incarnation.
It depends on a lot of factors, but mainly cost and yield.
Example; Apple didn't use any 7nm EUV variant in A12/A13. While Huawei used it for their SoC. Having said that MBCFET, or more commonly known as GAA was originally scheduled for 3nm in 2022, so giving another 2 year to bake should help.
So yes, if everything were executed to absolute perfection, then we should see a 2nm Apple Silicon in 2024.
Note: While Wccftech has gotten a lot better in the recent 12 months or so, I still wouldn't put them into reliable and trusted source. It is good for rumours and entertainment, but that is about it. ( Personally I would rather not have it appear on HN )
Chips don't really work like that. 99% of the cost is in R&D and factory development then the cost per chip is pretty low, you just have to average in the R&D cost right? Apple sells ~ 200M units every year and prior developments get rolled into low cost products. Each new process probably leads Apple to make at least 500M devices. At scale you can spend 10s of billions on R&D and be spending less than $15-25 per chip.
1.000 US$ no, but... I would not put it past Apple to make a literal system on chip. Like, one chip with everything on one die stack: CPU, GPU, RAM, cell modem, voltage regulators... the only external components would be ports and whatever cannot be reasonably expressed on a silicon die (e.g. coils for voltage regulators).
With this news, how much of a lead do they have over Intel now? When is Intel realistically going to ship their next node? Or is it all still perpetually delayed with no end in sight?
