I use atime to identify archives that can be retired. It's common for circuit designer to release a lot of large files for their peers to analyze or incorporate into a parent/grandparent simulation. They will use that data for as long as it is still relevant, which means different things for different types of data, and the only consistent thing we've found is that if the data hasn't been accessed in awhile, then we can retire it.
I guess maybe it’s the nonstandard sMEL chunk that bumps the size of the PNG file up so high. Seemed more to me that they were talking about an image of random noise though.
Tcl is more-or-less required if you're involved with the physical design of silicon (most EDA tools only provide a Tcl interface). It's a good fit for that purpose. If you need a language which is easy to embed and you want non-programmers to be able to use it, Tcl is a good choice, though I've heard that Lua has supplanted Tcl for that purpose.
Our flow is thousands of lines of Tcl code around all the cadence and synopsys tools. Then we write more Tcl to create the power grid, create blockages, etc.
In the silicon industry it’s definitely tcl only. Zero Lua. But every tcl script I have seen is extremely simple, often just a bunch of commands to the EDA tool that reads like a list of bash commands.
Tcl scripting gets more interesting when you want to talk to a design running in an FPGA over JTAG. I have a toy CPU project which I've so far tested on Altera/Intel, Xilinx and Lattice FPGAs, and a debug interface where a C-based ncurses debugger connects over TCP/IP to a Tcl bridge which talks to the appropriate JTAG interface for the particular type of chip.
I'm also a big fan of the full-fat Tk-capable Tcl in Altera's SignalTap / Virtual JTAG - I used it recently to plot histograms on-demand for profiling RAM / Cache accesses.
John Green, author of "The Fault in Our Stars", "Turtles All the Way Down", "The Anthropocene Reviewed", and other fine books is releasing a book called "Everything is Tuberculosis." If you are interested in the topic or just like to read well-written prose, I recommend joining me in pre-ordering it.
Intel bylaws state that the CEO has to retire at age 65. Pat will reach that age in March 2026. I haven't seen anyone being groomed to take the lead in 18 months, so I am concerned that the leadership transition will be jarring.