This LANai v11 RISC chip seems to be the successor of the LANai v7 and LANai v9 chips described here: https://www.myricom.com/scs/myrinet/...ogramming.html for which the gcc toolchain already exists: https://github.com/myri Porting this to LLVM makes more sense.

Nothing too interesting, as it doesn't use IBM's 7nm or Intel's 10nm chip tech. Just a simple but parallel high-speed network chip, as used in the Myrinet network cards. The old ones ran with 33MHz but very low latency.

Really exciting would be the Power8 based on IBM's new 7nm, which would finally blow away Intel advantages on an fully open (and unbackdoored) design.

Nothing about the POWER8 or IBM's process technology implies unbackdoored. I can't inspect the factories, or their supply chain, or the HDL they used, or the tools that processed the HDL. The only thing more "open" about POWER8 is firmware in some deployments, and maybe licensing the ISA (if you have enough clout/money to join the foundation, I can't find any licensing information at all). RISC-V is more interesting in every way, with respect to openness.

> Really exciting would be the Power8 based on IBM's new 7nm, which would finally blow away Intel advantages on an fully open (and unbackdoored) design.

Sounds like you read https://raptorengineeringinc.com/TALOS/prerelease.php :-)