The Zeppelin (Ryzen 1xxx) die is 212 mm2 and its CCXs are 88 mm2 leaving 124 mm2 for the uncore. Now we see that the Matisse (Ryzen 3xxx) IO die is 122 mm2 — virtually the same size on the same process for the same functionality. (I don't see how L4 cache would fit in there BTW.)
As to why it's so large, I guess connecting cores, memory, and PCIe at extremely high speed just requires a lot of transistors. Intel's uncore seems to be far smaller; I'm not sure how or why.
The Ryzen chips offer more PCIe lanes and ECC memory support. These chips also use the Infinity Fabric high-speed interconnect, which is not needed by Intel's single-chip designs. The two CCX units in Zeppelin also need to talk to each other, so probably all this complexity just adds up.
I thought the main reason is that AMD still needs to use GF's manufacturing capacity (according to their Wafer Supply Agreement) and it also makes the chiplet design cheaper (the high-performance node is only used where it really matters).
That could also be true. I remember from an adoredtv video it was mentioned that IO transistors are much harder to scale down. The guy certainly seems to do his research and know his stuff, but I suppose at the end of the day it is a youtube video. I have not checked into this myself, just taking adoredtv's word at face value.
I think that was poetic license on his part. Mobile SoCs and modems are scaling quite well on 7nm. The IO chip is already low enough power for desktop/server applications and is small enough for good yield. 7nm would just be more cost for no gain. And using 14nm allows AMD to meet the WSA. Otherwise they probably would have done a TSMC 16nm IO die and kept their entire supply chain in Asia.
Well, it's on a more mature node, which at least should mean better yields. It also probably doesn't benefit from a node shrink as much as the actual CPU, so throw it on old node so it's cheaper kind of deal.
EDIT: I got some stuff mixed up. This post is all wrong.
It's supposedly one IO fits all. It has to interconnect up to 8 CPU chips and 4-8 memory channels (and allegedly some L4 cache). It has to support 128 PCIe lanes (maybe more for the upcoming generation) too. Then also, it's 14nm, so things aren't as small.
I imagine that they laser out most of the die to save power on consumer chips.
