That stuff is great. Once in an embedded SW shop I received some prototypes routed like that. It was unexpected! I couldn't stop smirking and showing it off to everyone around :)
Let me modify that correct response by saying it's a company that writes firmware for embedded processors. They are not necessarily small: I've worked on embedded systems that used multiple Pentium-class processors that distributed the hard real-time work to a few dozen smaller (8 and 16-bit) processors.
How do you ensure the proper requirements for routing analog circuits, high-speed digital circuits, or RF circuits are satisfied in a freestyle routing?
My only problem with the auto router (in EAGLECAD at least) is that it ruined your undo/redo history! So basically if it screwed up you had to tear the entire thing up, or go back to an old save.
I had the opportunity to try out a bunch of them, including Altium in the late aughts and I was struck by how much worse the user interface got the more expensive the EDA software was. Eagle, free for student use, was the only one where when you used the mouse wheel to zoom it zoomed with respect to the mouse pointer location instead of the center of the screen. If they supported mouse wheel zooming at all.
I concur! They are all highly complex pieces of software each with years of design cruft and their own foibles. I've yet to try any of the "heavyweight" ones like Altium because I don't have a megacorp footing the bill, but certainly of The free ones they all have issues. I personally like and use kicad but agree that it still has some serious usability issues (though a LOT of progress has been made with >5.0) it has some features that i wouldn't give up for the world (push and shove routing for one) and some I despise (library management still blows) and on balance I prefer it to the restrictions of eagle (free) but for knocking up a quick board, easy eda is pretty handy to have on hand wherever I may be that I can't install the others on. it's full featured enough to not suck as much as (say) fritzing
I designed a PCB with KiCad in 2014-2016, with version 4.x and then had to make another one in late 2017, and gave KiCad another spin and am absolutely mind-blown as to how awesome it has become. I even opened up my old designs from '14 and they just worked, some complaining about an old version, but it got all the footprints (lots of custom ones, too!) right and I could just pick up and continue.
I'm not sure how KiCad scales up to the $10k+ EDAs, but I am thoroughly amazed at it's quality and useability, especially considering that it's FOSS.
I dunno, I think it's way past that because no human would/could do anything complex that looked like that. What's the word for when computers do something that looks weird but is actually just way better than what you could come up with?
Here's a paper that shows reflections (Fig. 3, "S11") and insertion loss (Fig. 4, "S12") on coplanar waveguides, when using a sharp 90° bend, a 90° bend with a champfer and the case where the bend is replaced by two successive 45° turns ("final design").
I'm a chip designer and this article kinda cracked me up. For microwave signals on submicron lines, losses get very significant. It seems that PCB design inherits our practices in places these issues aren't so critical.
But then I wonder about applications. If you ignore this rule of thumb, and gang a few hundred boards together sharing a clock... will your signal survive?
Sometimes a 'superstition' is just common sense regarding edge cases - walking under a ladder won't have cosmic effects, but a dropped bucket of paint can leave a mark
That or using discontinuities in impedance intentionally. I've designed and had built a handful of successful UHF planar PCB filters using Sonnet. In a lot of them I use very small changes in trace width as the place to put resonating elements. ie, http://superkuh.com/stepped-impedance-bandstop-filter.html
The difference between square corners and compensated is real. And it gets more real if you're working in generic FR4 with 1.6mm thickness and 2-3mm wide traces for the sweet spot between 50 and 75 ohms.
You can play around with this type of simulations quite easily. Have been using free version of Sonnet planar EM solver [1] for this over the years. Helpful in developing the industry standard magic RF intuition.
The "final design" is the chamfered bend with additional vias, a design with two 45° bends was not studied in this paper. Page 2, second paragraph of section A :
> The final design that includes both the chamfered bend and the vias
What I've been taught during my EE studies, is that the main reason to avoid square traces is for EMC reasons, mainly due to reflections due to the hard boundaries. Interesting that the article doesn't touch on that.
PCB design/layout is one of the more important factors influencing EMC. Taking it into account early in the PCB design phase saves you a lot of trouble during certification.
Yeah, it dances around the corners. Pun aside, signal reflections are the main reasons not to do it in high bandwidth circuits. Other circuits may have different reasons.
I'm surprised about the hand-wavy way of ignoring a very well understood phenomenon.
Reflections are caused by changes in impedance, not direction. The impedance at a 90° corner changes because there is more area which increases capacitance.
Pads are much longer than the width across the smallest corner, so if it gets rounded a little, there's no problem. But a 90° corner for the thinnest trace is vulnerable to being etched from all sides and getting too thin.
There are a lot of good technical arguments raised here but the real reason we don't use right-angle bends on the 90% of PCBs which aren't carrying serious current or running at GHz is that right angles look ugly.
Another important consideration is ease of routing signals during design. Using 45 degree corners in general produces pretty space-efficient routing that makes it easy to cluster signals together as well as move them if necessary during layout.
One point the article left out is the risk of traces lifting off of the board. Having less sharp corners seems to reduce the risk of this happening with components that have a mechanical risk of coming off (like USB connectors, or large capacitors).
Square corners seems likely to be less space efficient, which is one consideration of pcb design. Why we don't use round corners or fluid traces might be a better question.
Round corners are nice but the radius is constantly increasing so they do not stack as well as 45 degree corners. This is especially difficult when you have to move a group of signals together during design!
Acid trap was the one I kept hearing, and proved true on my home-etched PCBs. The 90-degree traces would get undercut but the 45-degree ones were fine.
To be fair it's less likely to be an issue with more advanced etching processes, but there are still limits. The thicker the copper layer, the wider your minimum track and gap widths become, otherwise the copper traces are excessively undercut.
I don't know about PCB level, but on smaller scales you should avoid making right-angle turns in metal lines because of electromigration [1]. Energetic electrons flowing along the line will crash into the 'wall' at the turn, and will knock the atoms out of place a little bit. Over time, this will lead to 'erosion' of the corner.
> on smaller scales you should avoid making right-angle turns in metal lines because of electromigration
Someone needs to tell the semiconductor industry that, then, because all traces inside a modern IC are at 90 degrees. The whole chip is just a big array of parallel lines in two orientation that get cut by photolithography to form circuits. The vias between levels are 90 degrees too, of course.
It's certainly true that electromigration is going to concentrate more at tight bends. But in practice if it isn't killing your 7nm interconnect you're... probably going to be fine with that 1 mil trace that is a million times wider.
The reason it isn't killing that 7nm interconnect is that those semiconductor physical implementation designers run lots of EM simulations to determine the reliability and lifetime of all traces, taking into account the trace dimensions, electrical properties and the expected current flows and the design is only signed off when those metrics meet or exceed the design requirements.
Note also that specialized metals (tungsten, ruthenium) are used on really fine lower level traces of advanced nodes, due both to their resistance to EM as well their better compatibility with silicon (smaller passivation thickness).
I think you missed the sarcasm. Electromigration is simply not an issue for PCB design, period. The relative scales of the devices are separated by many orders of magnitude. The effect wasn't even discovered until photolithography pushed scales to values much smaller than we see on even the tiniest printed circuit.
Maybe, just maybe, there's a high current, high voltage board out there with tiny traces that was designed with some kind of trivial electromigration mitigation. But if there is, I've never heard of it. And electromigration is absolutely not a reason to avoid 90 degree turns on your digital logic board, don't be ridiculous.
Electrochemical migration is an issue in high-rel PCBs, though I don’t think that is true electro migration from charge carriers. Silver and tin dendrites have failed satellites.
Yeah, different things. Electrochemistry involves motion of charge carriers through some kind of medium, and can happen over very large distances even if the medium is just the polymer surface of the board. And needless to say it doesn't care about junction angle at all.
"Electromigration" is the motion of individual conductor nuclei out of the wire due to scattering with electron momentum. Effectively, when electrons are asked (by the electric field in the conductor) to make ultra-sharp turns at nanometer scales, they sometimes collide with the aluminum/copper/tungsten/whatever nucleus instead, knocking that nucleus away from where it should be in the crystal. Over time, this erodes the junction, increasing electrical resistance, and eventually the chip starts to fail at voltages and clock rates it used to handle well.
Yeah, poor wording on my part. You're not going to be able to avoid 90-degree corners in any case when 45-degree (or any other non-axis-aligned) lines are not allowed in designs for many processes. What I should have said is that the metal line widths should take electromigration into account.
There are also fun things like optical proximity correction [1], but of course these things are mainly handled automatically by simulations/EDA tools now.
> Someone needs to tell the semiconductor industry that, then, because all traces inside a modern IC are at 90 degrees.
This occurs almost never in a modern VLSI process.
Practically every 90 degree turn in a modern process involves a via or a contact to a different layer--VLSI tends to run different layers in orthogonal directions from one another.
I actually suspect that the really advanced processes nowadays actually ban 90 degree turns in their design rules as it may make the phase shift masks impossible to compute.
Uh... a via IS a 90 degree turn. We live in a universe with three spatial dimensions.
The wording was loose, but I stand by the point: there are no interconnect technologies in the modern world that use anything but axis aligned conductors. All turns are 90 degrees. (It's just that to turn 90 degrees in the plane of the wafer you need to make two of them)
> The reason we don’t see square traces in most PCB designs is simply due to aesthetic convention. If it looks wrong, it is wrong. There is no specific reason why every circuit board design should shy away from 90-degree angles on traces, it’s just something that you shouldn’t do because it looks wrong.
It does matter for RF, as TFA says. So the tools do it for you. Since it's automatic and easily done with the tools, everyone just does it.
Sure, you don't have to shy away from 90° but you also don't have to avoid it. I strongly disagree with "looks wrong". It's simply an aesthetic choice, there is no right or wrong about it.
I wonder if they did this kind of optimization back in the day when traces were hand-taped. The sensitivity is to rise time, not actually frequency, so even for the slower designs of the day, maybe 45° or arced corners were still useful?
Huh, article says not to worry about traces unless dealing with 100 MHz+ signal lines.
Isn't that very common? Hell even the MSP430 is running at 25 MHz these days.
And for all the other reasons listed in the article, you should avoid sharp corners. It's lazy to do otherwise when mitred 45 degree bends or curves are so easy to generate in a CAD tool. It's the hardware version of a code smell - the board house (compiler) might not care, but it should be fixed - don't give up freely obtained manufacturing slack because you couldn't set up a trace bend rule.
I kind of feel like PCB layout ought to just be done by the antenna engineers for any serious product with wireless comms or high speed I/O.
On microcontrollers nothing external to the processor is running at that sort of rate. Even the clock is typically multiplied up many times so you won't tend to see >100MHz lines.
QSPI Flashes typically have ~50MHz line which is quite common, but not much else.
OK, but it's not just the clock rate that enters into the decision, one must also consider the rise-time of the edges.
If you're using, for example, a fast logic family like LVC, fast edges on badly routed traces can radiate and interfere with other parts of the circuit, even if you're dealing with "low" clock rates or simple un-clocked logic.
Yes, the rule of thumb for low frequency square wave clocks (a few GHz or less) is that your trace, routing, and connectors should all support up to the 5th harmonic, or 5 times the clock frequency. At higher frequencies the 5th harmonic is to high to realistically achieve, and you start to see reliance on sine wave clocks or heavy use of equalization to remove clock distortion from the trace. This applies for digital buses as well. If anyone is curious about how traces impact data throughput, I highly recommend they look up eye diagrams.
100 MHz in traces is very uncommon for typical DIY PCBs. The only place I can think you'd get that is in a microcontroller clock, but most people use modules or internal clocks.
It's not just the fundamental frequency that matters -- a square wave with fast edges will have harmonics which lead off to a surprisingly high frequency. Even on fairly slow signals they can be into the tens or hundreds of MHz.
The image at the top of the article shows a number of traces that look like they're trying to climb a steep hill. I don't know much about PCB design, so my best guess is that those squiggles are trying to match a certain latency. But if 90-degree turns are so meticulously avoided in the industry, why is it okay to do multiple 180-degree turns in quick succession?
Related: looking at the main image, there are lots of places where traces routinely deviate to go around a pad, with an extremely low clearance, needlessly so. The designer probably took a defensive approach: the traces have been routed to leave as much space as possible to easily allow additional traces in the same gap.
So to me this pcb is a rough draft, an unoptimized initial version. The optimization obviously wasn't worth any time (and I agree with that), but I think an EDA tool worth its price should take such a design and optimize it. Such details really aren't the job of a designer, but still have the potential to significantly improve a layout.
On this board it looks like just a functionality/beauty thing and does not matter much. But depends on the target. While for the pads I agree, spacing can be optimised, then for the densely routed areas space is your friend. At higher frequencies (shallow skin depth) most energy is guided by the trace, but transferred in the space. Traces become bounds of transmission lines along what transverse electromagnetic waves are propagating. This is the reason why dielectric constant and dielectric loss matter a lot at higher frequencies; and why good impedance matching is needed for efficient energy transfer. EMC/EMI/RFI is mostly energy management issue.
Um wait, the main reasons for I know about is, that square corners are a huge issue with higher currents, as they tend to burn from the inside out, due to the lower resistance in the corner and non equal flowing of electrons.
Electrons do bunch up on sharp corners, as far as high voltage design is concerned.
Sharp corners cause inductance when the current has to “turn the corner”. An infinitely sharp edge would have infinite inductance. Think of a charge having momentum, and the H field the result of that momentum. You can’t just change it.
This is more troublesome at RF due to the currents crowding at the edges of the line, where the path length is now different for inside and outside radius, irrespective of lumped discontinuities.
In the RF world we mitre the bends, and sometimes used swept bends. The swept bends supposedly radiate more than mitered, but have not proven that to myself.
The case where you do want sharp, 90 degree bends are on electrically small monopole type antennas. The inductance will compensate for the high capacitive reactance of the antenna.
Most have a Molex brand connector, though nothing > 50 VDC.
I use a lot of the Molex Pico-Lock connectors, and similar sizes; all board level stuff.
What I was revering to in the above post is the susceptibility to breakdown and corona discharge from sharp edges (example at link below). I have done some static E field modeling in CST for HV breakdown in potted modules.
For simple and slow communication busses on hobbyist boards, sure it probably doesn't matter.
But I really can't trust this very superficial attempt to prove a negative with regards to a very complex phenomenon that I do not think he understands, especially since he mentions nothing about inductance, reflections, or impedance changes.
Hell, RF experts with decades of experience will still find new corner-cases and issues with PCB layouts when it comes to analog signals.
In terms of "actual wisdom" regarding 90 degree traces: Some time ago at my job we had to actually scrap a PCB because of right-angle traces causing too much interference. The end effect was a comb filter on the signal and a ton of emitted RF interference.
TLDR: Yes, the phenomenon is real. Do not trust these hand-wavy attempts to dismiss it.
>a square of copper two millimeters on a side has the same resistance as a square of copper ten millimeters on a side. It’s counter-intuitive.
The phenomenon is perfectly intuitive for anyone who understands DC resistance of metals, and the geometric assumptions of the "sheet resistance" thought experiment.
Resistance is proportional to conducter length divided by cross-sectional area. For a sheet conductor, cross-sectional area is thickness times width. A necessary assumption, unstated in the article, is that the hypothetical test circuit somehow makes perfect, uniform electrical contact over the entirety of both of the sheet's chosen "width" edges.
TLDR "conventional" wisdom about square traces having adverse effects on introducing noise for high frequency lines turns out to be negligible. Instead square traces were/are frowned on because of acid pooling from the etching process for making PCBs.
