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> The M4 Max needs an enormous 512bit memory bus to extract enough bandwidth out of those LPDDR5x chips

Does M4 Max have 64-byte cache lines?

If they can fetch or flush an entire cache line in a single memory-bus transaction, I wonder if that opens up any additional hardware / performance optimizations.



> Does M4 Max have 64-byte cache lines?

on the CPU side: 64 bytes at L1, 128 byte cachelines at L2


A single memory transaction is almost always a 16n burst for LPDDR5x.




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