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Can you elaborate on the failure mode described here? If we take a model where registers (including PC) or memory can get bit-flipped, it seems like all bets are off.


High energy radiation causes single event upsets in digital logic when you get an unlucky hit in the right part of a circuit. When that part is a flip-flop holding state or a bus transmitting data, you get persistent corruption. That can cause any and everything to go awry or it may resolve itself depending on what was hit. Various design approaches are used to address these faults through redundancy mechanisms but it isn't always practical to employ them.

For basic software protection you may want to depend on a watchdog timer and filling unused memory with NOP slides to trap the processor until the timer reboots. If you have hardware controlling something more risky like explosive bolts, you may want stronger assurances that the hardware won't fail by adding lower level redundancies.


This is actually a pretty common part of the threat model for high integrity computing (e.g. the ECU in your car and airplane avionics). Part of the standard solution is to run processors in lockstep and throw errors if any part of the cpu state diverges between the cores.




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