Very valid question. The whole industry is trying to do it, mainly with the hope of increasing profit margins to SW levels. But there are fundamental issues that is in the way (this is valid for ASIC design):
- We only use models to simulate the chip, and this is at best partial. Verification coverage if the code is one thing. There are thousands of effects from power supply network to thermals, reliability (device aging, electromigration etc) and a bunch of analog stuff which has weird failure modes which is almost impossible to fully cover before shipping it. So, we never actually know what would fail before tapeout.
- Tapeour cost is immense. A full mask cost of an advanced node is easily $10 Million or more. You can always go to an MPW, but then they are rare for advanced nodes (1-2 times per year), putting an immense pressure on schedules.
- Chip production takes time. For old nodes ~3 months, advanced nodes it's getting close to ~5 months.
- Package design, test PCB design, their production takes a lot of time and money too. Typically package costs as much as the silicon to produce if the design is heavily IO limited and uses and advanced packaging solution.
- Lab test preperation and test itself takes time. Typically you would need months of test to get a meaningful picture of the issues. You woul need to go through temperature and voltage cycles, on/off cycles etc. This of course depends on the end application. Automotive and data centers are quite demanding.
- There is a lot of competition for pretty nuch the same product and there is a lot of vender lock-in as the customers don't want to redesign their system ever.
So at the end, if you are designing a complex ASIC, you will spend a lot of money and time per tapeout cycle. If you have a big issue, your customer will go to the next guy. You lost them for forever (or for this product cycle of 4-5 years, if you are lucky but that's death sentence for a start-up). Now you are tens of millions in negative without your main customer. Again, if you are lucky you can either find another customer or repurpose your design. This is increasingly difficult as complex chips often aim a narrow market. This makes everyone very risk averse, including your customers.
For less complex chips in old process technology nodes things can be sped up, and is already being sped up, by a lot of IP reuse or buying ready silicon proven IPs. The problem there is, the time to market isn't the determining factor anymore as anyone can make a functional chip relatively quickly, but what matters is who can do it cheapest. There's a reason why most audio codecs and 1Gbit ethernet PHYs in PCs are Realtek. This type of products aren't attractive for start-ups.
It's often a happy middle ground of these with a niche application which resonates well with the experience and the talent of the engineering team makes a good beginnings of a HW start-up. Even with the best team, you need minimum 2 years to show something though.
- We only use models to simulate the chip, and this is at best partial. Verification coverage if the code is one thing. There are thousands of effects from power supply network to thermals, reliability (device aging, electromigration etc) and a bunch of analog stuff which has weird failure modes which is almost impossible to fully cover before shipping it. So, we never actually know what would fail before tapeout. - Tapeour cost is immense. A full mask cost of an advanced node is easily $10 Million or more. You can always go to an MPW, but then they are rare for advanced nodes (1-2 times per year), putting an immense pressure on schedules. - Chip production takes time. For old nodes ~3 months, advanced nodes it's getting close to ~5 months. - Package design, test PCB design, their production takes a lot of time and money too. Typically package costs as much as the silicon to produce if the design is heavily IO limited and uses and advanced packaging solution. - Lab test preperation and test itself takes time. Typically you would need months of test to get a meaningful picture of the issues. You woul need to go through temperature and voltage cycles, on/off cycles etc. This of course depends on the end application. Automotive and data centers are quite demanding. - There is a lot of competition for pretty nuch the same product and there is a lot of vender lock-in as the customers don't want to redesign their system ever.
So at the end, if you are designing a complex ASIC, you will spend a lot of money and time per tapeout cycle. If you have a big issue, your customer will go to the next guy. You lost them for forever (or for this product cycle of 4-5 years, if you are lucky but that's death sentence for a start-up). Now you are tens of millions in negative without your main customer. Again, if you are lucky you can either find another customer or repurpose your design. This is increasingly difficult as complex chips often aim a narrow market. This makes everyone very risk averse, including your customers.
For less complex chips in old process technology nodes things can be sped up, and is already being sped up, by a lot of IP reuse or buying ready silicon proven IPs. The problem there is, the time to market isn't the determining factor anymore as anyone can make a functional chip relatively quickly, but what matters is who can do it cheapest. There's a reason why most audio codecs and 1Gbit ethernet PHYs in PCs are Realtek. This type of products aren't attractive for start-ups.
It's often a happy middle ground of these with a niche application which resonates well with the experience and the talent of the engineering team makes a good beginnings of a HW start-up. Even with the best team, you need minimum 2 years to show something though.