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FPGAs are implemented as tons of lookup-tables (LUTs). Basically a special kind of SRAM.



The thing about the LUT memory is that it's all accessed in parallel, not just a 64 bits at a time or so.


Not all, not always. FPGAs usually have more memory than is accessible in parallel (because memory cells are a lot cheaper than routing grid) and most customers want some blockram anyways. So what your synthesis tool will do with very high LUT usage is to do input or output multiplexing. Or even halving your effective clock and doubling your "number" of LUTs by doing multi-step lookups in then non-parallel memory.




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